The present invention relates to a semiconductor memory device, in which a plurality of memory cells having storage capacitor are arranged to provide a memory array.
In recent years, semiconductor memory devices have advanced rapidly toward higher and higher integration, especially in the case of dynamic RAMs.
FIG. 1a is a diagram showing a plan view of a conventional cell array of a DRAM, and FIG. 1b is its cross-sectional view along line A-A' of FIG. 1a.
At the surface of a p-type Si substrate 1, a field oxide 2, a capacitor insulator 3 and a cell plate (common capacitor electrode) 4 are formed as shown in FIG. 1b. For the surface of the capacitor area, a n.sup.+ -region 5 is formed. Also, on a gate insulator 6, a gate electrode 7 (word line) is stacked. The numbers 8 and 9 denote a n.sup.+ -source and a n.sup.+ -drain, respectively. Onto the substrate, a CVD SiO.sub.2 layer 10 is deposited. A bit line 11 of A1 contacts the drain 9 through a contact hole in CVD SiO.sub.2 layer 10. The cell plate 4 is expressed as a doted area in FIG. 1a and FIG. 1b.
In such high integrated DRAM devices, the soft-error caused by .alpha.-particles has become an intensive problem. Therefore, despite the desire of high integration, in order to assure this soft-error tolerance together with the requirements of enough sensitivity in sense circuits, the amount of storage charge cannot be excessively reduced.
One of the methods to preserve the capacitance of the memory cell, preventing the increase of the real estate per cell, is to make the capacitor insulator thinner. As for the 1M bit DRAM, 100.about.150 .ANG. of an SiO.sub.2 layer is used as the capacitor insulator. However, the dielectric strength of the capacitor insulator becomes a problem if the voltage of the cell plate is set to the ground voltage V.sub.ss or to the supply voltage V.sub.cc. This is because the maximum electric field arising in the capacitor insulator reaches 5 MV/cm. Hence, by using a thinner insulator, it is required that one use a medium voltage, namely (1/2) V.sub.cc, as the cell plate voltage.
FIG. 2a shows the equivalent circuit of the memory cell, and FIG. 2b shows its C-V curve against several cell plate voltages V.sub.cc. The numeral V expresses the storage voltage. As shown in FIG. 2b, in the case of the (1/2) V.sub.cc, the maximum voltage arising in the capacitor insulator can be maintained at about 2.5 volt in spite of the fact that the memorizing voltage V is kept at 5 volt.
However, along with this technique another problem occurs as is described in the following.
In the cell plate voltage generating circuit, the resistance division construction, is used such that resistors are connected between V.sub.cc and V.sub.ss. With regard to the cell plate voltage generating circuit, in order to prevent malfunction it is necessary to suppress fluctuations of the cell plate voltage which are caused by the capacitor coupling with the cell nodes. In order to accomplish such suppression, it is desirable to reduce the resistivity of the dividing resistors. However, power dissipation increases in the case of resistivity reduction, a clearly undesirable effect.